On Dec 15, 10:08 am, chrisv <chr... (AT) nospam (DOT) invalid> wrote:
I'm sure the internal debates were raging quite early, but the fact of
the matter is that it took them quite a long time to come to the
decision to go with the Pentium-3-derivative. I'm sure the Pentium 4
advocates were asking for several more second chances to get that turd
working right for the intervening 3 years, and they couldn't do
anything about it. So it really in the end, it doesn't matter whether
it was clear to them early or not, the only thing that matters is that
they simply couldn't get to a decision in any less than 3 years. There
was some anecdotal evidence that even the Pentium-M without the Core 2
desktop-specific enhancements would've kept them somewhat competitive
with AMD for the past 3 years. It was simply a matter of Intel allowing
people to officially create Pentium-M derived desktop motherboards.

Of course on the other side, they didn't have time to enhance Pentium M
with the AMD64 instructions yet, so the only processors that had them
were the Pentium 4-based chips from the Prescott generation forward.
During those early days, 64-bit was still quite the selling point
differentiator.

Yousuf Khan

On Dec 15, 10:08 am, chrisv <chr... (AT) nospam (DOT) invalid> wrote:
I'm sure the internal debates were raging quite early, but the fact of
the matter is that it took them quite a long time to come to the
decision to go with the Pentium-3-derivative. I'm sure the Pentium 4
advocates were asking for several more second chances to get that turd
working right for the intervening 3 years, and they couldn't do
anything about it. So it really in the end, it doesn't matter whether
it was clear to them early or not, the only thing that matters is that
they simply couldn't get to a decision in any less than 3 years. There
was some anecdotal evidence that even the Pentium-M without the Core 2
desktop-specific enhancements would've kept them somewhat competitive
with AMD for the past 3 years. It was simply a matter of Intel allowing
people to officially create Pentium-M derived desktop motherboards.

Of course on the other side, they didn't have time to enhance Pentium M
with the AMD64 instructions yet, so the only processors that had them
were the Pentium 4-based chips from the Prescott generation forward.
During those early days, 64-bit was still quite the selling point
differentiator.

Yousuf Khan

chrisv wrote:

Bob Colwell, formerly the Chief Architect for NetBurst, has said quite
a good deal publicly about the history of the design. One might winkle
out a trail of bread crumbs by trying to find any reaction at all to
his claims from anyone else associated with Intel, but I don't remember
seeing any such reaction. Insert story about Intel employee fired on
the spot for idle chatter to a seat mate on a commercial airline
flight.

In any case, Colwell claims that the purpose of NetBurst was, as many
have suspected, to get the clock speed up, because Intel had decided
that clock speed, not performance, was what the public would buy. To
preserve his own dignity, one imagines, Colwell has also claimed that
it was fundamentally a sound design and that he always expected to
perfect the architecture to get the kind of performance of which he
thought it capable.

The rest of the story one can guess at with some assurance: with the
Prescott fiasco, Intel grasped that the clock speed game, whatever its
marketing value, was over, and with it any motivation for pursuing
NetBurst. One doesn't have to take one's own inferences about Intel in
isolation. The entire industry seemed surprised by what happened at 90
nm. That there would have been those saying "I told you so" means
nothing. There have been those predicting various kinds of "brick
walls" for a long time, and a consistent bet against the pessimists
would have produced a long run of winning bets.

There seems to be something in the story for everyone: Intel was (it is
claimed) proceeding from a cynical marketing decision and not from
sound engineering, Intel managed to get away with it for a while, even
engineers working for Intel have self-respect, and, in the end,
physics, not marketing, gets the last word.

None of this marks Intel out as peculiar. The history of the industry
is littered with the burned-out wreckage of companies that stubbornly
stuck with an insight with a limited lifetime and limited value to
begin with. Microsoft and Intel are both wallowing around in the mud
of their own success, as IBM apparently once did. At this point,
though, only the most wild-eyed believers in, say, Google or AMD would
predict that Intel or Microsoft is another DEC (or even an IBM) waiting
to happen. IBM remains; Amdahl, DEC, and Compaq are gone; Intel and HP
feed off the carcasses.

Robert.

Keith, you are making a rather extraordinarily claim. SMT became a
well defined term in the mid 1990's due to the work of the SMT group at
UW. I have read several of their research and I haven't found a single
reference to such a beast. Certainly, academics have a responsibility
when submitting refereed papers to cite and discuss prior work.

If you look at "simultaneous multithreading: maximizing on-chip
parallelism", the seminal paper, particularly section 7, I see no
mention of such a processor from IBM (although I did not read all the
papers referenced, merely looked for titles indicating IBM or the 195).
Given the folks that the SMT group collaborated (including Joel Emer
of DEC), I have a hard time believing that they simply 'forgot' the
existence of a prior processor which implemented all the key features
of SMT. There were some processors that implemented SMT, but they were
special purpose (ray tracing), lacking caches, etc. etc.

All together, it seems to me that the burden of proof rests upon your
shoulders to show:
1. What the 195 is.
2. That it actually implemented SMT

You have done neither, and rather indicated that "I need to ask
elsewhere". It seems to me that if you wish to debunk what seems to be
reasonably well accepted truth, you should be willing to back up, with
references...rather than simply claim the existence of a counter
example without substantiation.

DK

Del Cecchi wrote:
My apologies if I mischaracterized your statement. The point remains:
certain elements within IBM clearly did not believe that SOI was worth
it, and wanted to stick with bulk.

Perhaps our definition of high end vary...

This was information from an engineer in Canada who used to post to
comp.arch. I have no particular reason to disbelieve what he said,
although I'm certainly open to listening to other POVs. I believe I've
already indicated that I'm not an EE, physicist nor do I run sims. I
would point out that there is some information on the relative merits
of the different processes:

http://www.realworldtech.com/page.cf...005001504&p=14

This article, written by David Wang, shows a cross comparison of
different process technologies. In looking at the 65nm nodes, we can
compare the IBM process to the joint IBM/AMD/Toshiba/Sony. It appears
that the Ion for ITSA is slightly higher, while Intel's Ioff is about
2x lower. Of course, Intel's high Vt transistors have substantially
less leakage (factor of ~10) than the low Vt, at the cost of worse Ion
performance.

If I made any errors in reading the chart, I'd be more than happy to
accept corrections.

Also, for those who were curious about SRAM cell sizes, they are
included in the chart.

The chart above does have some information, and the rest of the article
has more. One caveat is that I'm not sure whether these numbers
include the later modifications to the process.

It's a rather useful educational tool. Word processing, spread sheets,
email, wikipedia, developing. All sorts of things you can do.

DK

In article <1166320159.677262.136960 (AT) f1g2000cwa (DOT) googlegroups.com>,
dkanter (AT) gmail (DOT) com says...
You still can't get it right! You certainly are blind.
Moving the goal-posts again. Why am I not surprised.
You admit that you're nothing but an Intel gad-fly? At least
you're being honest today.

Do you know what this means? I didn't think so.

Different strokes for different folks.

Of course you don't know. You have no degree in anything relevant,
remember?

It's a *USELESS* educational tool, for anything other than learning
how to use a computer. PC's aren't likely to teach a third-world
farmer how to increase his crop yield. He has more important
things to learn than WinBlows.

--
Keith

In article <1166318701.327115.25380 (AT) 80g2000cwy (DOT) googlegroups.com>,
dkanter (AT) gmail (DOT) com says...
New terms are what academia is all about. Have you researched the
/195? I suggest that you do. "New" things tend not to be so new,
just the costs come down.

Why not look at the "micro"-architecture of the /195? The Dual I-
Stream isn't so much different. Two instructions streams from the
I-box being fed into the E-box so it had something to do if either
'I's took a branch.

/95.

Do some more research. SMT, as you narrowly define it? Maybe not.
here is little new under the sun though. Perhaps you'd like to
follow Intel's SMT patents backwards?

No, I'm calling out your typical technology "expertise" crap and
telling you to look further. You can't, not that you'd understand
it anyway.

--
Keith

krw wrote:
According to Del "As Keith knows, there was a heated debate within IBM
over the merits of
SOI. And today the IBM Fab manufactures both bulk and SOI."

That there was a debate clearly means that some folks had differing
views on the merits of SOI. Now at the conclusion of the debate, the
doubters were either overruled or convinced of the merits of SOI.
However, just because the outcome went one way at IBM does not
guarantee that the outcome will go the same at Intel.

There are plenty of companies that design MPUs, DSPs, etc. etc. and
their processes vary quite a bit. Some have more metal layers, some
have less, some use SOI, some don't. If you think I'm so blind perhaps
you could enlighten us all with your knowledge and explain what I'm
missing?

[snip]

Keith, most of the terms are defined (perhaps informally, but defined
nonetheless) earlier in the article.

This point went back to earlier in the thread when discussing SRAM
density.

You know, some of the best computer architects I've spoken with don't
have relevant degrees. Take John McCalpin; he got a PhD in Physical
Oceanography. Now that sounds irrelevant to computer architecture, but
last time I heard he did some good things at SGI, at IBM and now at
AMD. Besides, I rather doubt you know enough about my academic
background to make judgments.

DK

krw wrote:
I tried looking into the /195, but there's not much online about it.
The only reference I can find is a paper: JO Murphey, RM Wade -
Datamation, 1970

Which is not available online. Given the date, it's clearly a dead
tree journal, and probably one that hasn't been OCRed.

So the idea is that on a long latency event, you switch to another
process or thread? This sounds like a precursor to switch on event
multithreading.


The SMT research at UW clearly was influenced by prior efforts. They
cited quite a few of them in the paper I mentioned. I didn't see
anything on the 195 in their paper. Now perhaps the connection is 2nd
degree or 3rd degree. However, it seems to me that SMT likely focuses
on addressing different performance issues than what the 195 was faced
with. Are the ideas similar? Somewhat. But AFAICT they are quite
different beasts. It sounds like the dual istream is far more similar
to SoEMT than SMT.

DK

On 16 Dec 2006 17:49:19 -0800, "David Kanter" <dkanter (AT) gmail (DOT) com> wrote:

If you look back at what you posted, Intel is apparently considering SOI
for the 32nm and 22nm nodes. Ther appears to be a umm, dichotomy in your
reasoning here.

With all due respect to Dave Wang, somtime around the time of that article,
Dave stated categorically right in this NG that we would never see SOI 65nm
from Chartered... and now??

From what I've observed, the most useful part of PCs/Internet for students
is as a tool for plagiarism...and theft.:-(

--
Rgds, George Macdonald