George Macdonald wrote:
big help to joe dugan in LDC, eh?

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

George Macdonald wrote:
Not really. When I say SOI, I mean PD-SOI. Intel plans to use FD-SOI,
which is a rather different beast. No dichotomy there...

How does that matter? David's numbers can all be checked against the
IEDM presentations/papers AFAIK. The numbers say it all...

DK

On 18 Dec 2006 20:24:42 -0800, "David Kanter" <dkanter (AT) gmail (DOT) com> wrote:

<snigger>

The point is kinda clear - he was totally off the mark on SOI and its
accessability to a foundry. As for SOI, it's my understanding that, like
many other subjects of study, it's what is *not* in published papers which
matters to getting it "right". The "numbers" are only one point in time!

--
Rgds, George Macdonald

You don't seem to appreciate the difference between FD and PD SOI. As
I understand it, there are rather substantial differences; for instance
FD doesn't suffer from the floating body effect as bad (although it
appears that short channel effects can worsen). The bottom line is
that just because Intel plans to use SOI in the future:
1. Does not mean it will happen - Intel planned to have a 10GHz CPU
out by now, plans always can change
2. Does not mean that the SOI process Intel uses will be similar to
the AMD/IBM one - they may skip PD-SOI altogether, and opt for fully
depleted SOI.

Either way, there is clearly no universal truth regarding the benefits
of SOI.

It's not clear to me exactly how the Chartered/AMD/IBM deal evolved.
with demand for older parts), so it's not clear how much R&D chartered
really spent. If the deal was "IBM/AMD give chartered process tech"
that's a little different than "Chartered pays up 1/3 the cost of R&D".

Also, just because David was wrong about whether a foundry would use
SOI does not mean his hard numerical data, which comes from refereed
papers is invalid.

Sure, reading papers won't necessarily tell a random knowledgeable
person how to implement a PD-SOI process. However, they will tell
someone what results they can expect to achieve in terms of performance
benefits. What they won't say is the implementation costs, which are,
as I indicated, probably more important for Intel than for others.
Their business model has always focused on providing fairly high
performance MPUs at very attractive prices; this is in direct contrast
to say, DEC, which focused on the highest performance.

That's certainly true, and I'd expect the numbers to change a bit.
However, I haven't heard any compelling evidence why the performance
for a PD-SOI process would change more (or less) than a bulk process
over time. A priori, my expectation would be that the amount of
improvement over time is equal or perhaps varies with the quantity
produced.

DK

On 19 Dec 2006 14:57:22 -0800, "David Kanter" <dkanter (AT) gmail (DOT) com> wrote:

What you don't seem to umm, appreciate is that the IBM/AMD process has been
in full proven production in several SOTA fabs for 3 years now... and well
in to production ramp on its 3rd iteration.

That you trot out two diametrically opposed cases in one post and then try
to cover it up with speculative maybe this & maybe that, only demonstrates
what a dither you are in. This is complex stuff which is only fathomable
and "known" by a few people - pretending to have deep insights into further
developments is just so much journo-babble .

Hmm, it clearly spanked Intel for a while! The symmetry SOI allows for DSL
was clearly a winner.

Seems like you've taken such a high "vantage point" that the clouds have
obscured your view. If you were paying attention, you'd know that the
"older parts" story is just another red herring.

It seems clear that he did not have close to a good handle on how well
developed the process was nor its amenability to what Intel calls "Copy
Exact". An autopsy on the hows and whys is a waste of time.

You're missing the point. Especially in the light of the Moto fiasco, what
the the papers "tell" is that with all the variables in the right place, it
can be done and (the talent at) IBM knows how.

Quantum leaps my son!

--
Rgds, George Macdonald

George Macdonald wrote:
I'm failing to see how this is an argument for Intel using PD-SOI....

No, I'm pointing out a number of reasons why you are wrong. That some
of the reasons are mutually exclusive is irrelevant...you'd still have
to overcome both objections.

It's really not that hard to understand: partially depleted != fully
depleted. Intel expressed interest in FD SOI, not PD SOI.

Here's a link for you, straight from the horses mouth:

http://www.intel.com/technology/maga...hr-qa-0806.pdf

See page 4:

What about other manufacturers' use of "silicon on insulator"
(SOI)?
Intel's superior transistor performance and leakage have been
achieved by meticulous engineering of "bulk CMOS"
techniques, which offer the highest performance and best value to our
customers. SOI adds substantial costs and
complexity to the process. A comparison of published transistor
switching speeds shows Intel's bulk transistors to have
faster switching speeds at comparable leakage currents compared to the
best published numbers on SOI transistors. A
more troubling issue is that SOI has higher "thermal resistance"
than bulk CMOS. As a result, SOI transistors are forced
to run at temperatures higher than necessary. Higher operating
temperatures could cause long-term reliability problems.
So does Intel rule out SOI completely?
No. There is a type of SOI called fully depleted (FD-SOI) that has
merits beyond the partially depleted SOI that some
of our competitors are using today. FD-SOI has been under active
evaluation for some time at Intel.

That's from the head of process development at Intel.

That's a good one: AMD certainly was ahead of Intel for a while, and
now you're trying to argue that this is due to their process
technology? Maybe you forgot about uarch?

There's nothing stopping Intel from using strained silicon with bulk.

You're ignoring the point: did chartered pay for R&D, or just receive?
There's a whole world of difference.

DK

On 21 Dec 2006 14:38:18 -0800, "David Kanter" <dkanter (AT) gmail (DOT) com> wrote:

I have not said they would or should - you're now arguing with some
imaginary entity.

Umm your attempt to cover your dual turd up has not worked!

Apparently too hard for you to even grasp the degree of difficulty of
either. Again you're inventing a strawman you can argue over.

And Intel has not done production SOI so they have the opinion of a
bystander - their feeble attempts to belittle others' success is given the
lie by the past 3.5 years of floundering. Bottom line: Intel knows no more
about IBM/AMD's process than IBM/AMD knows about theirs.

The above little diatribe lives in blissful ignorance -- one would assume
results of their lab work -- of the fact that IBM/AMD's SOI process has
been running cooler for years now. Hate is a powerful emotion... one which
clouds the focus... and apparently leads to the issuance of blind
propaganda. Believe it if you wish

The evidence is clear from the results. That you would argue this only
clarifies your "gad-fly" status.

Yes, they eventually got it working in some fashion - it's a nastier
straining problem though. I'd have thought that from the many available
diagrams this would be obvious to someone without a Chemistry background...
but maybe not. Intel *did* fall behind on this and the parallel delays and
evential clock speeds in their different 90nm uarchs was some evidence of
this.

Oh, BTW did they pay up on the patent license on straining yet?;-)

Irrelevant. Are you now going to tell that "Copy Exact" is nothing... a
mere detail?... or is it another Intel coup? Reproducing a fab plant is no
simple matter - even repeating is hard enough. That an independent foundry
could be whipped into *advanced* shape in relatively short order speaks to
the success of the process & methods... otherwise why did DaveW suggest it
could not happen??

--
Rgds, George Macdonald

George Macdonald wrote:
Then what is your point about the IBM/AMD fabs having used SOI for
several years regarding? I'm sorry if I didn't make the connection.

Again, I don't think Intel's past 3.5 years of floundering have
anything to do with process related issues. Intel's 130nm products
were quite competitive with AMD's; at 90nm, I certainly agree that
Intel's server and desktop offerings were looking anemic. However,
their mobile offers look quite good. It's hard to say how Intel's 65nm
parts will play against AMD's...but right now they look to be doing
quite well based on preliminary data. Given that the bag is decidedly
mixed, I find it hard to see any evidence that Intel's problems in the
last 3-4 years were process related as you implied earlier.
Microarchitecturally related: absolutely. But I can find no fault in
the process folks.

I don't recall claiming anything of that nature, rather, I claimed that
PD-SOI does not appear to have made sense for Intel's process,
production, etc. etc.

Perhaps you could provide proof that "IBM/AMD's SOI process has been
running cooler for years now."? I have yet to see any...and try to
remember, your claim has to do with process only, not
microarchitecture.

I certainly don't take Dr. Bohr's words at face value, rather I take it
as rather decisive proof that Intel finds PD-SOI unattractive, but
FD-SOI much more interesting...as I claimed before.

I don't think so.

Let's say that only process and uarch impact performance/heat/power.

Suppose chip A is 20% faster (or cooler) than chip B. You're claiming
this implies the process that chip A was manufactured in is faster (or
cooler) than the process for chip B. I don't think this is reasonable.
Suppose the microarchitecture for chip B is so inefficient that it
reduces speed by 30% (or increases heat/power draw by 30%) then it
would turn out that the process for B was actually 'better'.

My point is you have not conducted any analysis indicating that a SOI
process is 'better', the numbers for 65nm certainly don't seem to
support it. Moreover, you haven't accounted for the additional cost of
SOI wafers, redesigning circuits to use SOI friendly techniques, yield
losses due to increased fragility, etc. etc.

I don't think so, they were all capped due to frequency.

Quite frankly this whole tangent is irrelevant. David's numbers are
quite solid. If you have proof they are wrong, please show it. Rather
than casting aspersions on the data in the article by claiming that the
author made a mistake once upon a time.

DK

On 22 Dec 2006 21:54:29 -0800, "David Kanter" <dkanter (AT) gmail (DOT) com> wrote:

The connection is that you are posting contadictory info/opinion. See my
1st post in the thread for one example. Another is that "And frankly, SOI
is worth less and less performance at every node" along with the fact that
you said Intel is considering SOI for 22nm & 32nm. You try to wriggle out
of both by separating PD from FD... after the fact. You just can't seem to
help panning AMD's direction while praising Intel's but the reasoning is
all twisted to hell.

Intel's P4 uarch was supposed to be designed for the higher speeds -
apparently the process could not deliver. The Dothan P-M had the same
delay as the P4, while they sorted out the process and if you look back,
the P-M and derivatives have been stuck at <=2GHz for 3 years now. I'd
have to assume the process plays some part in this umm, stall.

And yet you want to believe all the Intel anti-SOI propaganada.

The proof is all around - it's been common knowledge and I have provided
the "proof" several times now. You just don't listen and I'm not going to
repeat myself again!

NIH is a powerful driver. Negative propaganda is ugly.

Quite a tangled web you're weaving there.

Quite how you've missed the fact that the P4 is known as a "heater" boggles
the mind. Even the anal...ysts talk about it daily. Blaming it on the
uarch, when the two are supposed to be designed to work in unison, is a
complete red herring.

Yup - even the P-M has been capped for several years now... until the most
recent releases... but it had nothing to do with the process?Ô_õ

It's no claim, e06oo3$7as$1 (AT) grapevine (DOT) wam.umd.edu and I cast no aspersions
- another of your strawmen. The fact is that the data is not supported by
the palpable results.

--
Rgds, George Macdonald

George Macdonald wrote:
George, you are certainly welcome to think whatever you wish. My
opinions remain as they always have. AMD's choice to implement PD-SOI
makes sense (even in face of decreasing benefits), because it should
(in theory) ensure that their MPUs perform better on the same node. If
AMD performed worse than Intel on the same node, they would be in
rather serious trouble, since Intel should have a performance and cost
advantage half the time, when they are a node ahead.

I think it's also relatively clear that it doesn't make sense for Intel
to pursue PD-SOI. This should hardly be surprising since Intel and AMD
are rather different companies, with rather different emphasis in their
business models. In engineering, there is rarely a one size fits all
solution...

The issue wasn't with the process. I've heard reasonably good accounts
from engineers inside Intel and that was not the problem.

I don't recall the length of delays on prescott and Dothan so I'm not
going to comment on that. However, simply making that assumptions
seems rather simplistic; after all, if a single product showed good
improvements, that would disprove your argument.

You're misrepresenting my position. I think that given AMD's
competitive position, it made a lot of sense to pursue PD-SOI.
However, it's very clear that it makes no sense for Intel to pursue
PD-SOI. This doesn't mean PD-SOI sucks, or is evil, or inefficient.
It merely means that the trade-offs are more suitable for IBM and AMD,
but not Intel.

When I say proof, I mean actual hard evidence...not just 'everyone
knows it'. Not so long ago, everyone knew that Ford and Nixon were not
super friendly...Besides, if it is common knowledge that AMD and IBM
have a cooler process and it has been so for years, I'm sure you can
come up with proof to back that up.

Of course I'm not going to listen when your proof consists of "well
everyone knows that".

I think it shows quite clearly that simply because a uarch which uses a
given process is superior does not imply that the process itself is
superior. Hence, examples which rely on microarchitectural comparisons
are irrelevant.

What's your point? That the P4 ran hot is not evidence that Intel's
process runs hot. It is evidence that a specific uarch, known to use a
lot of power runs hot. Hardly surprising.

Not at all. You are assuming that Intel codesigns their uarch and
processes. I haven't seen any evidence of that, and in fact, most of
the evidence I've seen indicates that the relationship between the two
are far from equal. Remember, Intel bills itself as the largest
semiconductor manufacturer. Nothing about MPUs there... By all
accounts, process folks really have primacy there.

You have mentioned two products. What about Xscale, what about
chipsets? What about everything else that goes on 90nm? Are they all
frequency capped?

So you just believe that Intel, AMD and IBM all present made-up numbers
for refereed conferences? A much more reasonable conclusion would be:
There are other variables at play.

DK