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Re: What "Parallel Hz" Really Is
Hardware Chips Processor, cache, memory chips, etc. (comp.sys.ibm.pc.hardware.chips)
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#1
 
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Re: What "Parallel Hz" Really Is -
05-12-2006
, 09:59 PM
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Isn't this like taking double/quadruple pumped bus and pipelining to the extreme? --- Sounds like it, doesn't it? I've got a feeling he doesn't know what he's talking about, tho... |
PpPQuote:
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Hey, little lost angel, welcome back. Where ya been? |
I've been busy with study and work. Work's mostly design/programming &
marketing leaving very little time to pursuit side hobbies like
electronics. For a while I dropped off the radar on Usenet totally
having had to spend more time tracking local web forums for marketing
purposes and only been back in csiphc for a few months.
Hopefully I'll have some time to drop into seb/sed to bug you guys
with more innate noobish ee questions on some stuff I've been
wondering about
PPp<trimmed followup NG>
--
A Lost Angel, fallen from heaven
Lost in dreams, Lost in aspirations,
Lost to the world, Lost to myself
#2
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On Sun, 14 May 2006 17:56:50 +0200, Tarjei T. Jensen wrote: Rob Warnock wrote: The PDP-8/I was fully-parallel, just like the PDP-8, except that it was the first of the "-8" line to use TTL logic levels (+3V & 0) instead of the negative ones (-3V & 0) used in the Classic -8. [It was built out of "M-Series" modules, rather than the "R/S/T/B-Series".] Interesting stuff, indeed. I'm certainly not a DECie, so remembered wrongly. ;-) I thought TTL was +5V and 0. Or was this a later development? The TI 74xx TTL series had a power supply of 5V and gnd (signal levels of ~3.6V and .8V), but that wasn't the only TTL ever to be done. IBM's TTL, used in the 3080s, was +1.25/-3V with a signal level of gnd to -1.5V, IIRC. TTL is a circuit topology, rather then a specific product. BTW, most "TTL" wasn't. The later series ('S', 'AS', 'ALS', 'F', and even 'LS' were actually SDTL). My bet is that the DECs were DTL too, though I'd love to hear more from Rob. ...maybe continue thos over on AFC. -- Keith |
#3
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"Keith" <krw (AT) att (DOT) bizzzz> wrote in message news an.2006.05.14.23.17.56.143556 (AT) att (DOT) bizzzz...On Sun, 14 May 2006 17:56:50 +0200, Tarjei T. Jensen wrote: Rob Warnock wrote: The PDP-8/I was fully-parallel, just like the PDP-8, except that it was the first of the "-8" line to use TTL logic levels (+3V & 0) instead of the negative ones (-3V & 0) used in the Classic -8. [It was built out of "M-Series" modules, rather than the "R/S/T/B-Series".] Interesting stuff, indeed. I'm certainly not a DECie, so remembered wrongly. ;-) I thought TTL was +5V and 0. Or was this a later development? The TI 74xx TTL series had a power supply of 5V and gnd (signal levels of ~3.6V and .8V), but that wasn't the only TTL ever to be done. IBM's TTL, used in the 3080s, was +1.25/-3V with a signal level of gnd to -1.5V, IIRC. TTL is a circuit topology, rather then a specific product. BTW, most "TTL" wasn't. The later series ('S', 'AS', 'ALS', 'F', and even 'LS' were actually SDTL). My bet is that the DECs were DTL too, though I'd love to hear more from Rob. ...maybe continue thos over on AFC. -- Keith The 74s for sure was ttl not dtl. I'm not sure about 74LS. |
timeframe. Even the 'LS family may be half TTL and half DTL.
--
Keith
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Keith <krw (AT) att (DOT) bizzzz> wrote: +--------------- | Tarjei T. Jensen wrote: | > Rob Warnock wrote: | >> The PDP-8/I was fully-parallel, just like the PDP-8, except | >> that it was the first of the "-8" line to use TTL logic levels | >> (+3V & 0) instead of the negative ones (-3V & 0) used in the | >> Classic -8. [It was built out of "M-Series" modules, rather | >> than the "R/S/T/B-Series".] .... | > I thought TTL was +5V and 0. Or was this a later development? | | The TI 74xx TTL series had a power supply of 5V and gnd (signal | levels of ~3.6V and .8V)... +--------------- Technically, yes. I was just rounding off for simplicity. And your 3.6V/0.8V aren't quite correct, either. The 3.6 was a "typical" high output; the minimum guaranteed output voltage was less. IIRC, the actual 74xx levels were these: Power supply: +5.0 V +/- 0.25 V [4.75 - 5.25] Maximum high output level: 5.0 V [actually, ~5.6 or so.] "Typical" high output level: 3.6 V Minimum high output level: 2.4 V Maximum high input level: 2.0 V "Typical" input threshold: ~1.5 V Minimum low input level: 0.8 V Maximum low output level: 0.4 V Minimum low output level: 0.0 V [actually, ~-0.6 or so.] As you can see, there's about 0.4 "noise margin" between what an output driver must drive and what a receiver input must accept. Also, when driven low, TTL inputs sourced substantial current (typ. -1.6 mA per "unit load") which had to be sinked by the outputs. [When driven high, inputs sinked a much smaller current, ~100 uA, IIRC, so a fairly-light static current source ("pullup resistor") was needed on "open-collector" or "tri-state" busses.] +--------------- | BTW, most "TTL" wasn't. The later series ('S', 'AS', 'ALS', 'F', | and even 'LS' were actually SDTL). My bet is that the DECs were | DTL too, though I'd love to hear more from Rob. +--------------- Nope, the original M-Series boards were indeed classic 74xx TTL, *very* low density, e.g., IIRC, an M206 card comprised only two 7474 chips -- only four flip-flops! Later cards may have used some 'LS or 'S chips, and definitely added more MSI parts to the earlier SSI-only mix. -Rob ----- Rob Warnock <rpw3 (AT) rpw3 (DOT) org 627 26th Avenue <URL:http://rpw3.org/ San Mateo, CA 94403 (650)572-2607 |
that happened to still be in my cabinet, it has been resolved. Regular
74xx, 74Hxx, were TTL. 74Sxx was mostly TTL but had some DTL in complex
functions. 74LS was DTL. Some devices also had PNP emitter follower
inputs on some pins.
--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”
#5
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In article <ihtj62pu0a43nc8tcjorqagd96hkq4lrma (AT) 4ax (DOT) com>, chrisv (AT) nospam (DOT) invalid says... Keith wrote: On Mon, 15 May 2006 00:29:08 +0100, Pooh Bear wrote: Weren't the shottky ( and derived ) parts DTL input and TTL output ? Shottky diode logic (thus properly DTL) with a shottky clamped totem-pole output (not part of "TTL"). IIRC, the origonal 74S series was still TTL (multiple emitter inputs). It's been too long to remember where the split was made though. ;-) I'm pretty darn sure that 74XXXX is all TTL. The S and LS series were just enhancements with shottky transitors (i.e. shottky clamped transistors) but they are still TTL. No, the later versions have schottky diode logic with schottky clamped amplifier rather than transistor (emitter) logic (74S series also had the schottky clamped amplifier). Circuit diagrams (note: from rusty memory) TTL (74xx and 74Sxx): Vcc | .-. Vcc | | Vcc | | | .-. '-' | | | | |/ | | +---+-| Q3 '_' | | | | | ----- |/ V A1 0----vv \-----| Q2 - A1 o----/ Q1 |> +-------o O | |/ +----+| Q4 | | .-. | | | GND | | '-' created by Andy´s ASCII-Circuit | v1.22.310103 Beta www.tech-chat.de GND Schottky clamped TTL has schottky diodes from base to collector on Q2 and Q4 (IIRC) to prevent saturation. SDTL (74LSxx, 74ASxx, 74ALSxx, etc.): VCC VCC | .-. VCC .-. | | | | | | | | | '-' |/ '-' + -| | | | | | | A1 o-S<--+ |/ V +--->S-----| - A2 o-S<--+ |> +--- O | |/ +--| | | .-. | | | GND | | '-' | GND Again, Q2 and Q4 are schottky clamped. The pullup device was often a darlington rather than a npn and a diode |
--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”
#6
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Keith wrote: In article <ihtj62pu0a43nc8tcjorqagd96hkq4lrma (AT) 4ax (DOT) com>, chrisv (AT) nospam (DOT) invalid says... drawings snipped |
Quote:
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The pullup device was often a darlington rather than a npn and a diode I didn't think so because the output current was limited to |
limiting (B^2 *3.6/Rc2).
--
Keith
#7
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In article <4cuejfF17l8e7U1 (AT) individual (DOT) net>, cecchinospam (AT) us (DOT) ibm.com says... Keith wrote: In article <ihtj62pu0a43nc8tcjorqagd96hkq4lrma (AT) 4ax (DOT) com>, chrisv (AT) nospam (DOT) invalid says... drawings snipped The pullup device was often a darlington rather than a npn and a diode I didn't think so because the output current was limited to ~B(3.6/Rc2). With a darlington there wouldn't be much current limiting (B^2 *3.6/Rc2). -- Keith They usually put a small resistor in series with the pull up device(s) |
is at work.
#8
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Keith <krw (AT) att (DOT) bizzzz> wrote: +--------------- | Schottky clamped TTL has schottky diodes from base to collector | on Q2 and Q4 (IIRC) to prevent saturation. +--------------- The TI 54/74Sxx series [and competitors] also used Schottky clamping on Q1 [the input transistor] as well -- yes, even those with multiple-emitter inputs. They also used Schottkys for the Darlington driver of the upper output stage [which you didn't show -- it would have driven your Q3's base] and for the anti-overdrive transistor [also not shown] clamped on the base of Q4. In fact, of the six transistors in the small 54/74Sxx series, only the one matching your Q3 was *not* Schottky-clamped. ;-} -Rob ----- Rob Warnock <rpw3 (AT) rpw3 (DOT) org 627 26th Avenue <URL:http://rpw3.org/ San Mateo, CA 94403 (650)572-2607 Adding the schottky diodes was easy. All you had to do was allow the |
collector(epi).
--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”
#9
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"Keith" <krw (AT) att (DOT) bizzzz> wrote in message news:MPG.1ed3d0f9c858ef85989a54 (AT) News (DOT) Individual.NET... In article <4cuejfF17l8e7U1 (AT) individual (DOT) net>, cecchinospam (AT) us (DOT) ibm.com says... Keith wrote: In article <ihtj62pu0a43nc8tcjorqagd96hkq4lrma (AT) 4ax (DOT) com>, chrisv (AT) nospam (DOT) invalid says... drawings snipped The pullup device was often a darlington rather than a npn and a diode I didn't think so because the output current was limited to ~B(3.6/Rc2). With a darlington there wouldn't be much current limiting (B^2 *3.6/Rc2). -- Keith They usually put a small resistor in series with the pull up device(s) for short circuit protection. 40 ohms as I recall for S. But the bible is at work. Yes, the darlington and curent limters are clear in the drawings |
(bottom two):
http://www.ee.washington.edu/stores/...4ls/74ls00.pdf
--
Keith
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