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What core speed were/are north bridges and/or MCH's clocked at?
Hardware Chips Processor, cache, memory chips, etc. (comp.sys.ibm.pc.hardware.chips)
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#21
 
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Re: What core speed were/are north bridges and/or MCH's clocked at? -
11-07-2006
, 05:12 PM
#22
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pigdos <NA (AT) nowhere (DOT) com> wrote: : Um, nothing writes to memory unless the CPU initiates it. DMA : xfers are not initiated without CPU intervention (at least to : set up the starting and ending addresses). I'm referring here : to a single CPU situation w/a N. Bridge. 1. You are top posting....learn how to communicate in Usenet or get the f**k off this channel! 2. You're actually going to argue with Daytrip?? AH HAHAHAHAHAHAHAHAHAHA!!!! |
most of his answers are cogent and on point (in this thread at least),
but i don't see him as a figure to be revered as handing out the word
on MPU or chipset design.
DK
#23
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jack wrote: pigdos <NA (AT) nowhere (DOT) com> wrote: : Um, nothing writes to memory unless the CPU initiates it. DMA : xfers are not initiated without CPU intervention (at least to : set up the starting and ending addresses). I'm referring here : to a single CPU situation w/a N. Bridge. 1. You are top posting....learn how to communicate in Usenet or get the f**k off this channel! 2. You're actually going to argue with Daytrip?? AH HAHAHAHAHAHAHAHAHAHA!!!! Who is day tripper? Why is he such an authority? I recognize that most of his answers are cogent and on point (in this thread at least), but i don't see him as a figure to be revered as handing out the word on MPU or chipset design. DK |
/daytripper (...it sounds too much like actual work ;-)
#24
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jack wrote: 2. You're actually going to argue with Daytrip?? AH HAHAHAHAHAHAHAHAHAHA!!!!Who is day tripper? Why is he such an authority? I recognize that most of his answers are cogent and on point (in this thread at least), but i don't see him as a figure to be revered as handing out the word on MPU or chipset design. DK |
- Ken
#25
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Um, nothing writes to memory unless the CPU initiates it. DMA xfers are not initiated without CPU intervention (at least to set up the starting and ending addresses). I'm referring here to a single CPU situation w/a N. Bridge. |
*large* cluestick!
BTW, you have been but the hurt apparently hasn't set in yet.
--
Keith
#26
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jack wrote: pigdos <NA (AT) nowhere (DOT) com> wrote: : Um, nothing writes to memory unless the CPU initiates it. DMA : xfers are not initiated without CPU intervention (at least to : set up the starting and ending addresses). I'm referring here : to a single CPU situation w/a N. Bridge. 1. You are top posting....learn how to communicate in Usenet or get the f**k off this channel! 2. You're actually going to argue with Daytrip?? AH HAHAHAHAHAHAHAHAHAHA!!!! Who is day tripper? Why is he such an authority? I recognize that most of his answers are cogent and on point (in this thread at least), but i don't see him as a figure to be revered as handing out the word on MPU or chipset design. |
know who 'tripper is. ...some better than others. To quote your
boss, what a maroon!
--
Keith
#27
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In article <1162941226.420973.208990 (AT) h48g2000cwc (DOT) googlegroups.com>, dkanter (AT) gmail (DOT) com says... Who is day tripper? Why is he such an authority? I recognize that most of his answers are cogent and on point (in this thread at least), but i don't see him as a figure to be revered as handing out the word on MPU or chipset design. Who the fuck are you? |
search engine. One could ask the same of you...and there Google is
somewhat less helpful.
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A DeanK clone? The rest here pretty much know who 'tripper is. |
I don't, in case you missed that particular implication.
Nor am I inclined to accept some random anonymous person as an expert
in the field unless I am familiar with the work they have done and
their areas of expertise. Anyone can claim to know something about
chipsets or MPUs, but how many of those folks have taped one out...or
taped out a relevant product. Working on an embedded design does not
necessarily mean you know about high performance design on bleeding
edge process technology, just as experience designing high performance
MPUs does not imply knowledge about tweaks for low power and efficient
operation.
DK
#28
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krw wrote: In article <1162941226.420973.208990 (AT) h48g2000cwc (DOT) googlegroups.com>, dkanter (AT) gmail (DOT) com says... Who is day tripper? Why is he such an authority? I recognize that most of his answers are cogent and on point (in this thread at least), but i don't see him as a figure to be revered as handing out the word on MPU or chipset design. Who the fuck are you? I think it's pretty easy to find that out if you know how to use a search engine. One could ask the same of you...and there Google is somewhat less helpful. |
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A DeanK clone? The rest here pretty much know who 'tripper is. That's truly wonderful, why don't you give yourself a pat on the back. I don't, in case you missed that particular implication. |
closer attention.
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Nor am I inclined to accept some random anonymous person as an expert in the field unless I am familiar with the work they have done and their areas of expertise. Anyone can claim to know something about chipsets or MPUs, but how many of those folks have taped one out...or taped out a relevant product. Working on an embedded design does not necessarily mean you know about high performance design on bleeding edge process technology, just as experience designing high performance MPUs does not imply knowledge about tweaks for low power and efficient operation. |
you should pay attention to what 'triper says.
Quote:
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DK |
--
Keith
#29
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In article <1162959872.197451.134300 (AT) e3g2000cwe (DOT) googlegroups.com>, dkanter (AT) gmail (DOT) com says... krw wrote: In article <1162941226.420973.208990 (AT) h48g2000cwc (DOT) googlegroups.com>, dkanter (AT) gmail (DOT) com says... Who is day tripper? Why is he such an authority? I recognize that most of his answers are cogent and on point (in this thread at least), but i don't see him as a figure to be revered as handing out the word on MPU or chipset design. Who the fuck are you? I think it's pretty easy to find that out if you know how to use a search engine. One could ask the same of you...and there Google is somewhat less helpful. ...and I trust everything on the net? <guffaw A DeanK clone? The rest here pretty much know who 'tripper is. That's truly wonderful, why don't you give yourself a pat on the back. I don't, in case you missed that particular implication. He's de-cloaked here in .chips at least once. Maybe you should pay closer attention. Nor am I inclined to accept some random anonymous person as an expert in the field unless I am familiar with the work they have done and their areas of expertise. Anyone can claim to know something about chipsets or MPUs, but how many of those folks have taped one out...or taped out a relevant product. Working on an embedded design does not necessarily mean you know about high performance design on bleeding edge process technology, just as experience designing high performance MPUs does not imply knowledge about tweaks for low power and efficient operation. There is a lot more to this biz than "taping out" an MPU. Perhaps you should pay attention to what 'triper says. DK DK == Dean Kent? |
Let us return to the question at hand - which I believe started with a claim
by "pigdos" that on systems sporting a north bridge the front side bus address
lines are "unidirectional" - from processor to bridge.
After making said claim, pigdos ran right through the stop sign labeled "cache
coherency" that was erected by Mr. Kanter (and supported by myownself).
pigdos' *reply* was "In a northbridge design the address lines would run one
way -- from the CPU to the N. Bridge."
When again challenged, he responded "Um, nothing writes to memory unless the
CPU initiates it. DMA xfers are not initiated without CPU intervention (at
least to set up the starting and ending addresses). I'm referring here to a
single CPU situation w/a N. Bridge."
Umm...Okay, so stipulated. Doesn't change a thing, of course.
Bottom line: I don't think pigdos understands the ramifications of processor
memory caches and IO devices that can initiate memory transactions.
I also don't think he knows about MSI....And what *that* means wrt fsb
transactions.
Thus, my conclusion stands: pigdos needs to do a LOT of homework before he
could even hope to hold up his end of the discussion.
/daytripper
(Of course, if he *did* the homework, that'd be the end of the discussion ;-)
#30
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On Wed, 8 Nov 2006 08:41:58 -0500, krw <krw (AT) att (DOT) bizzzz> wrote: Easy there, youngster ;-) It's a beautiful day today, let's not spoil it :-) |
--
Keith
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