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What core speed were/are north bridges and/or MCH's clocked at?
Hardware Chips Processor, cache, memory chips, etc. (comp.sys.ibm.pc.hardware.chips)
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#41
 
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Re: What core speed were/are north bridges and/or MCH's clocked at? -
11-09-2006
, 07:05 AM
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daytripper wrote: Easy there, youngster ;-) It's a beautiful day today, let's not spoil it :-) Let us return to the question at hand - which I believe started with a claim by "pigdos" that on systems sporting a north bridge the front side bus address lines are "unidirectional" - from processor to bridge. After making said claim, pigdos ran right through the stop sign labeled "cache coherency" that was erected by Mr. Kanter (and supported by myownself). pigdos' *reply* was "In a northbridge design the address lines would run one way -- from the CPU to the N. Bridge." When again challenged, he responded "Um, nothing writes to memory unless the CPU initiates it. DMA xfers are not initiated without CPU intervention (at least to set up the starting and ending addresses). I'm referring here to a single CPU situation w/a N. Bridge." Umm...Okay, so stipulated. Doesn't change a thing, of course. Bottom line: I don't think pigdos understands the ramifications of processor memory caches and IO devices that can initiate memory transactions. I also don't think he knows about MSI....And what *that* means wrt fsb transactions. Thus, my conclusion stands: pigdos needs to do a LOT of homework before he could even hope to hold up his end of the discussion. Indeed, I think everyone could agree to that. Even getting back to his main point (what frequency does the chipset run at internally), he needs to really rethink what is necessary. Now that he knows that as a rough approximation, the NB runs at the speed of the addressing pins on the FSB...he should try and figure out how that can work and why it is done that way. |
--
Rgds, George Macdonald
#42
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In article <1163015914.865846.213000 (AT) k70g2000cwa (DOT) googlegroups.com>, dkanter (AT) gmail (DOT) com says... Could be, but I don't follow every thread religiously, nor do I really You are a simple pimple. You are like glue to this NG. It's your reason for living! |
DK
#43
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krw wrote: In article <1163015914.865846.213000 (AT) k70g2000cwa (DOT) googlegroups.com>, dkanter (AT) gmail (DOT) com says... Could be, but I don't follow every thread religiously, nor do I really You are a simple pimple. You are like glue to this NG. It's your reason for living! Uh huh...I think you need to get out a little more. |
--
Keith
#44
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Let us return to the question at hand - which I believe started with a claim by "pigdos" that on systems sporting a north bridge the front side bus address lines are "unidirectional" - from processor to bridge. After making said claim, pigdos ran right through the stop sign labeled "cache coherency" that was erected by Mr. Kanter (and supported by myownself). pigdos' *reply* was "In a northbridge design the address lines would run one way -- from the CPU to the N. Bridge." When again challenged, he responded "Um, nothing writes to memory unless the CPU initiates it. DMA xfers are not initiated without CPU intervention (at least to set up the starting and ending addresses). I'm referring here to a single CPU situation w/a N. Bridge." Umm...Okay, so stipulated. Doesn't change a thing, of course. Bottom line: I don't think pigdos understands the ramifications of processor memory caches and IO devices that can initiate memory transactions. I also don't think he knows about MSI....And what *that* means wrt fsb transactions. Thus, my conclusion stands: pigdos needs to do a LOT of homework before he could even hope to hold up his end of the discussion. /daytripper (Of course, if he *did* the homework, that'd be the end of the discussion ;-) |
#45
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Um daytripper, how do you figure a hard drive unilaterally writes to main memory? Do you honestly think devices just independently begin writing to main memory (aside from memory NIC's) without any CPU intervention at all? Have you ever read up on what exactly is involved in setting up a DMA xfer? |
The CPU writes into some controller register the address range it might use.
Thats all. The device is then allowed to start transfer at will (for example
disk might start transfering the data after 15ms -- by that time typical OS
will switch task about 15 times as well -- probably whole CPU cache will be
swapped few times as well and CPU has already executed about 30 million
instructions.
The data disk writes into memory must get in sync with CPU caches, and how
do you thing the CPU is informed about data being written?
No, no cache flushing instruction and stuff is done when disk finishes
tranfer, as performance would be terrible.
Hint: google for memory snoops.
There are only two viable options: either address bus is bidirectinal
(Pentiums & Cores and stuff) or there is additional snoop access bus (K7).
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There is also the concept of uncacheable memory addresses maybe you should read up on that as well. |
The areas where disk transfers occurs are cacheable in any hald-baked OS!
Such areas are typically for some controller memory and/or io ports mapped
into CPU's physical address range. Uncacheable memory area is needed when
memory accesses must be stricly controlled (for example accessing to some
address triggers some action in the device).
rgds
--
Sebastian Kaliszewski
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"Never underestimate the power of human stupidity" -- from Notebooks of L.L.
#46
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Um daytripper, how do you figure a hard drive unilaterally writes to main memory? Do you honestly think devices just independently begin writing to main memory (aside from memory NIC's) without any CPU intervention at all? |
intervention is required by the PCI BusMastering spec.
Depending on how the OS wishes to use resources and the
intelligence of those peripherals, many things are possible.
Video card GPUs set-up and run almost all the DMA.
High-performance ethernet does likewise (except zero-copy).
-- Robert
#47
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Um daytripper, how do you figure a hard drive unilaterally writes to main memory? Do you honestly think devices just independently begin writing to main memory (aside from memory NIC's) without any CPU intervention at all? Have you ever read up on what exactly is involved in setting up a DMA xfer? There is also the concept of uncacheable memory addresses maybe you should read up on that as well. |
#48
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Um daytripper, how do you figure a hard drive unilaterally writes to main memory? Do you honestly think devices just independently begin writing to main memory (aside from memory NIC's) without any CPU intervention at all? Have you ever read up on what exactly is involved in setting up a DMA xfer? There is also the concept of uncacheable memory addresses maybe you should read up on that as well. |
While I don't use killfiles, I suspect our sun will burn out before I try to
help you again...
/daytripper
#49
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On Mon, 06 Nov 2006 09:46:55 -0500, daytripper <day_trippr (AT) REMOVEyahoo (DOT) com wrote: On Fri, 03 Nov 2006 18:55:58 GMT, "pigdos" <NA (AT) nowhere (DOT) com> wrote: I've always been curious about this because these devices have to bridge multiple types of buses. Intel's Blackford MCH chipset, for example, has a "core clock" (aka ""BCLK") of either 250, 266, or 333 mhz, depending on FSB "speed" (1000, 1066 or 1333mhz, respectively). No internal multiplier? Then I'm missing something here, unless there's 128-bit or dual 64-bit paths internally, it doesn't seem to jibe that data is arriving and leaving at 6.4GB/s but is clocked internally at 200MHz. Even so, it doesn't seem to make sense to clock FSB addresses at 400MT/s (again for a 200MHz BCLK) and then use a 200MHz clock for the internal logic. |
one. The FSB is quad-pumped, and the DIMM bus is double-pumped and
double-width. Data moves through the chip in 32 byte wide form, so the BCLK is
the right frequency for the core...
Cheers
/daytripper
#50
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The existance of CPU intervention isn't proof that such intervention is required by the PCI BusMastering spec. Depending on how the OS wishes to use resources and the intelligence of those peripherals, many things are possible. Video card GPUs set-up and run almost all the DMA. High-performance ethernet does likewise (except zero-copy). -- Robert |
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